Digital/analog converter circuit

ABSTRACT

A selection section ( 105 ) selects a step voltage, among a plurality of step voltages (SV 1 , SV 2 , SV 3 , . . . ) each having a voltage value changing stepwise, corresponding to the digital value of digital data (D-DATA). For each of the plurality of step voltages (SV 1 , SV 2 , SV 3 , . . . ), different digital values are allocated to different steps of the step voltage. An amplifier section ( 106 ) amplifies the step voltage selected by the selection section ( 105 ). An output section ( 107 ) outputs the step voltage amplified by the amplifier section ( 106 ) as an output voltage (Vout) for a time period corresponding to the digital value of the digital data (D-DATA).

TECHNICAL FIELD

The present invention relates to a circuit for supplying an outputvoltage having a voltage value corresponding to the digital value ofdigital data, and more particularly to a digital/analog convertercircuit in a drive device for driving a liquid crystal panel and thelike having a load capacitance.

BACKGROUND ART

The mainstream of conventional digital/analog converter circuits hasbeen a type in which a reference voltage generation circuit using aresistance divider circuit generates a plurality of reference voltagescorresponding to the bit precision of digital data, a selector selects areference voltage, among the plurality of reference voltages,corresponding to the digital value of digital data, and the selectedreference voltage is supplied to a buffer. In this type, however, withenhancement of the bit precision, the circuit scale of the selectorincreases exponentially. It is therefore difficult to reduce the circuitarea of a high-definition driver. In particular, a liquid crystaldriver, which is required to achieve reduction in circuit area as wellas high definition and high gradation, has found difficulty inimplementing these requirements simultaneously.

To overcome the above problem, Japanese Laid-Open Patent Publication No.3235121 (Patent Document 1) gives the bit resolution along, not only thevoltage axis, but also the time axis to reduce the circuit scale of theselector. To state more specifically, a step voltage whose value changesstepwise is supplied to each of a plurality of reference voltage lines,a sampling switch circuit selects a step voltage, among the plurality ofstep voltages supplied to the plurality of reference voltage lines,corresponding to the digital value of the most significant bits ofdigital data, the selected step voltage is accumulated in a holdcapacitor, and the accumulated voltage is amplified with an outputamplifier and outputted.

Patent Document 1: Japanese Laid-Open Patent Publication No. 3235121DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention

However, since the sample/hold circuit composed of the switch (samplingswitch circuit) and the capacitor (hold capacitor) is placed upstream ofthe buffer, the capacitor constituting the sample/hold circuit must havea sufficiently large capacitance value (normally, several pF) forsuppression of switch field through noise. Hence, the time constant inthe signal path from a reference voltage generation circuit to theoutput buffer increases by the sample/hold circuit. This delays theresponse of the output voltage, possibly producing a difference betweenthe voltage value (target voltage value) corresponding to the digitalvalue and the voltage value of the actually outputted voltage (settlingerror).

The time constant in the signal path from the reference voltagegeneration circuit to the output buffer may be reduced by reducing theresistance value of the sample/hold circuit. In this case, however, thesize of the switch will become large to reduce the ON resistance of theswitch, and with increase of the switch size, the switch field throughnoise may increase. To suppress increase of the switch field throughnoise, the capacitor must have a large capacitance value. This will notonly increase the circuit scale but also increase the time constant.Hence, the originally intended effect of reducing the time constant willbe small. As another means for reducing the time constant in the signalpath from the reference voltage generation circuit to the output buffer,considered is reducing the resistance value of a resistance dividercircuit (ladder resistance) for generating reference voltages as thesources of step voltages. This will however result in increase of thethrough current in the resistance divider circuit causing increase ofthe power consumption. Hence, the conventional configurations finddifficulty in reducing the time constant in the signal path from thereference voltage generation circuit to the output buffer to reduce thesettling error.

With the progress toward higher definition and higher gradation, thesettling time for the output voltage become shorter. The voltage valueof the output voltage therefore fails to reach the target voltage valuecorresponding to the digital value, causing a settling error. If thesettling error becomes excessively large, the linear relationshipbetween the digital value and the voltage value of the output voltage isbroken, failing to secure the monotonous increase characteristic of theoutput voltage.

An object of the present invention is providing a digital/analogconverter circuit small in settling error. More specifically, an objectof the present invention is reducing the settling error by reducing thetime constant in the signal path from the reference voltage generationcircuit to the output buffer and/or enhancing the change rate of theoutput voltage.

Means for Solving the Problems

According to one aspect of the invention, the digital/analog convertercircuit generates an output voltage having a voltage value correspondingto a digital value of digital data and supplies the output voltage to aload capacitance as an object to be driven. The digital/analog convertercircuit includes: a selection section for selecting a step voltage,among a plurality of step voltages each having a voltage value changingstepwise, corresponding to the digital value of the digital data; anamplifier section for amplifying the step voltage selected by theselection section; and an output section for supplying the step voltageamplified by the amplifier section as the output voltage for a timeperiod corresponding the digital value of the digital data. For each ofthe plurality of step voltages, different digital values are allocatedto different steps of the step voltage.

In the digital/analog converter circuit described above, no sample/holdcircuit composed of a switch and a capacitor is provided between theselection section and the amplifier section, but a sample/hold circuitis composed of the output section connected downstream of the amplifiersection and the load capacitance as the object to be driven. Hence, thetime constant in the signal path from the step voltage supply source tothe amplifier section can be widely reduced. This can reduce the circuitscale and also speed up the response of the output voltage, whichresults in reduction in settling error. Also, when the object to bedriven is a liquid crystal panel, the load capacitance is normally aslarge as several tens of pF that is enough to neglect the influence ofswitch field through noise. In this case, therefore, the resistancevalue at the output section can be sufficiently reduced, and thus thetime constant from the output section to the load capacitance can bereduced.

Alternatively, the digital/analog converter circuit includes: aselection section for selecting a step voltage, among a plurality ofstep voltages each having a voltage value changing stepwise,corresponding to the digital value of the digital data; and an outputsection for outputting the step voltage selected by the selectionsection for a time period corresponding to the digital value of thedigital data. For each of the plurality of step voltages, differentdigital values are allocated to different steps of the step voltage, anda settling time for the first step of the step voltage is longer than asettling time for each of the second and subsequent steps of the stepvoltage. The output section may include: a voltage hold portion forholding the step voltage selected by the selection section; and anamplifier portion for amplifying the voltage held by the voltage holdportion and outputting the amplified voltage as the output voltage, forexample.

In the digital/analog converter circuit described above, the voltagevalue of the output voltage is allowed to reach the voltage value forthe first step of the step voltage within the settling time for thefirst step. Hence, the settling error can be reduced, and thus themonotonous increase characteristic of the output voltage can be secured.

Alternatively, the digital/analog converter circuit includes: aselection section for selecting a step voltage, among a plurality ofstep voltages each having a voltage value changing stepwise,corresponding to the digital value of the digital data; and an outputsection for outputting the step voltage selected by the selectionsection for a time period corresponding to the digital value of thedigital data. For each of the plurality of step voltages, differentdigital values are allocated to different steps of the step voltage, anda voltage value for the first step of the step voltage is higher than atarget voltage value corresponding to a digital value allocated to thefirst step. The output section may include: a voltage hold portion forholding the step voltage selected by the selection section; and anamplifier portion for amplifying the voltage held by the voltage holdportion and outputting the amplified voltage as the output voltage, forexample.

In the digital/analog converter circuit described above, the change rateof the voltage value of the output voltage can be increased in thesettling time for the first step of the step voltage. Hence, the voltagevalue of the output voltage is allowed to reach the target voltage valuecorresponding to the first step of the step voltage within the settlingtime for the first step, and thus the monotonous increase characteristicof output voltage can be secured.

Preferably, for each of the plurality of step voltages, voltage valuesfor the second and subsequent steps of the step voltage are higher thantarget voltage values corresponding to digital values allocated to thesesteps.

In the digital/analog converter circuit described above, the change rateof the voltage value of the output voltage can be increased in thesettling time for each of the second and subsequent steps of the stepvoltage. Hence, the voltage value of the output voltage is allowed toreach the target voltage values corresponding to the second andsubsequent steps of the step voltage within the settling times for thesesteps, and thus the linearity between the digital value and the voltagevalue of the output voltage can be further improved.

Preferably, the digital/analog converter circuit described above furtherincludes a settling time adjustment section for adjusting, for each ofthe plurality of the step voltages, the settling time for the first stepof the step voltage according to the magnitude of a time constant of theoutput voltage.

In the digital/analog converter circuit described above, the increase insettling error in the first step of the step voltage can be suppressed,and thus the monotonous increase characteristic of the output voltagecan be further secured.

Preferably, the digital/analog converter circuit described above furtherincludes an emphasis adjustment section for adjusting, for each of theplurality of the step voltages, the voltage value for the first step ofthe step voltage according to the magnitude of a time constant of theoutput voltage.

In the digital/analog converter circuit described above, the increase insettling error in the first step of the step voltage can be suppressed,and thus the monotonous increase characteristic of the output voltagecan be further secured.

Preferably, the digital/analog converter circuit described above furtherincludes an emphasis adjustment section for adjusting, for each of theplurality of the step voltages, the voltage values for the second andsubsequent steps of the step voltage according to the magnitude of atime constant of the output voltage.

In the digital/analog converter circuit described above, in which theemphasis amount for each of the second and subsequent steps of the stepvoltage is adjusted according to the change in the magnitude of the timeconstant of the output voltage, the improvement in the linearity betweenthe digital value and the voltage value of the output voltage can bemaintained.

Alternatively, the digital/analog converter circuit includes: aconversion section for converting the digital value of the digital datato a corrected digital value whose correspondence with the voltage valueof an actual output voltage is linear; a selection section for selectinga step voltage, among a plurality of step voltages, corresponding to thecorrected digital value of the digital data obtained by the conversionsection; and an output section for outputting the step voltage selectedby the selection section as the output voltage for a time periodcorresponding to the corrected digital value of the digital dataobtained by the conversion section. The output section includes: avoltage hold portion for holding the step voltage selected by theselection section; and an amplifier portion for amplifying the voltageheld by the voltage hold portion and outputting the amplified voltage asthe output voltage, for example.

In the digital/analog converter circuit described above, in which therelationship between the digital value and the voltage value of theoutput voltage is linear, the monotonous increase characteristic of theoutput voltage can be secured.

EFFECT OF THE INVENTION

As described above, the difference between the target voltage valuecorresponding to the digital value and the voltage value of the outputvoltage (settling error) can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a drive device of Embodiment 1 of thepresent invention.

FIG. 2 is a waveform diagram for explaining step voltages in the drivedevice of FIG. 1.

FIG. 3 is a view showing the entire configuration of a liquid crystaldisplay device.

FIG. 4 is a waveform diagram for explaining the operation of the drivedevice of FIG. 1.

FIG. 5 is a waveform diagram for explaining step voltages in a drivedevice of Embodiment 2 of the present invention.

FIG. 6A is a waveform diagram for explaining the output voltage forcomparison.

FIG. 6B is a waveform diagram for explaining changes in output voltagein Embodiment 2 of the present invention.

FIG. 7 is a graph for explaining the relationship between the digitalvalue and the output value of the output voltage in Embodiment 2 of thepresent invention.

FIG. 8 is a block diagram of a drive device of Embodiment 3 of thepresent invention.

FIGS. 9A and 9B are waveform diagrams for explaining the operation ofthe drive device of FIG. 8.

FIG. 10 is a waveform diagram for explaining a step voltage in a drivedevice of Embodiment 4 of the present invention.

FIG. 11 is a waveform diagram for explaining a step voltage in analteration of the drive device of Embodiment 4 of the present invention.

FIG. 12 is a block diagram of a drive device of Embodiment 5 of thepresent invention.

FIG. 13A is a view showing the correspondence between the digital valueand the voltage value of the output voltage. FIG. 13B is a view showingthe correspondence between the voltage value of the output voltage andthe corrected digital value. FIG. 13C is a view showing an example of alookup table.

FIG. 14 is a graph for explaining the relationship between the digitalvalue and the output value of the output voltage in the drive device ofFIG. 12.

FIG. 15 is a block diagram for explaining an alteration of Embodiment 2.

FIG. 16 is a block diagram for explaining an alteration of Embodiment 3.

FIG. 17 is a block diagram for explaining an alteration of Embodiment 4.

FIG. 18 is a block diagram for explaining an alteration of Embodiment 5.

DESCRIPTION OF THE REFERENCE NUMERALS

-   -   10 Drive device    -   101, 401 Reference voltage generation circuit    -   102, 302 Clock generation circuit    -   103, 303 Step voltage generation circuit    -   104 Latch circuit    -   105 Selection circuit    -   106 Buffer    -   107 Switch    -   110 Digital/analog converter circuit (DAC circuit)    -   20 Object to be driven (LC panel)    -   21 Load capacitance    -   131-1, 131-2, 131-3 Synthesis section    -   30 Liquid crystal panel    -   G1, G2, G3 Gate line    -   S1, S2, S3, S4 Source line    -   331 Switch circuit    -   501 Converter circuit    -   111 Capacitor

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings. Note that in thedrawings the same or equivalent components are denoted by the samereference numerals and description thereof will not be repeated.

Embodiment 1

FIG. 1 shows a configuration of a drive device of Embodiment 1 of thepresent invention. The drive device 10 includes a reference voltagegeneration circuit 101, a clock generation circuit 102, a step voltagegeneration circuit 103 and a digital/analog converter (DAC) circuit 110including a latch circuit 104, a selection circuit 105, a buffer 106 anda switch 107. The drive device 10 supplies an output voltage having avoltage value corresponding to the gradient (digital value) indicated ingradation data of n-bit precision (n is a natural number). The drivedevice 10 also selects a step voltage, among a plurality of stepvoltages each having a voltage value changing stepwise, corresponding tothe gradation data, and outputs the selected step voltage for the timeperiod corresponding to the gradation data. In other words, the drivedevice 10 gives the bit resolution along, not only the voltage axis, butalso the time axis.

The reference voltage generation circuit 101, composed of a ladderresistance, for example, generates a plurality of reference voltagescorresponding to the bit precision of gradation data D-DATA. In otherwords, the reference voltage generation circuit 101 generates 2^(n)reference voltages having 2^(n) voltage values (target voltage values)corresponding one-to-one to 2^(n) digital values.

The clock generation circuit 102 generates a clock signal CLK forcontrolling generation of step voltages and the output time periods forthe step voltages. Herein, the clock signal CLK includes, within onehorizontal period, a reference pulse for determining the start timing ofa step voltage and 2^(m) (m is a natural number; m<n) additional pulsesfor determining timing at which the voltage value of the step voltagechanges.

The step voltage generation circuit 103 generates 2^(n-m) step voltageseach having a voltage value changing in 2^(m) steps in synchronizationwith the clock signal CLK from the clock generation circuit 102. Morespecifically, each of 2^(n-m) synthesis sections 131-1, 131-2, 131-3, .. . of the step voltage generation circuit 103 receives 2^(m) referencevoltages among the 2^(n) reference voltages and sequentially selects the2^(m) reference voltages in ascending order of the voltage value insynchronization with the clock signal CLK.

The latch circuit 104 receives n-bit gradation data D-DATA, and outputsthe digital value of the (n−m) most significant bits of the gradationdata D-DATA to the selection circuit 105 and the digital value of mleast significant bits thereof to the switch 107.

The selection circuit 105 selects a step voltage, among the 2^(n-m) stepvoltages generated by the step voltage generation circuit 103,corresponding to the digital value of the (n−m) most significant bits ofthe gradation data D-DATA.

The buffer 106 amplifies the step voltage selected by the selectioncircuit 105 and outputs the amplified step voltage.

The switch 107 outputs the step voltage amplified and outputted by thebuffer 106 for the time period corresponding to the digital value of them least significant bits of the gradation data D-DATA from the latchcircuit 104. More specifically, the switch 107 outputs the step voltagefor the time period from the reference pulse of the clock signal CLK toan additional pulse corresponding to the digital value of the m leastsignificant bits of the gradation data D-DATA. In this way, an outputvoltage Vout having a voltage value corresponding to the digital valueof the gradation data D-DATA is supplied to a load capacitance 21 of aliquid crystal panel 20.

The step voltages will be described with reference to FIG. 2. To each ofthe 2^(n-m) step voltages to be generated by the step voltage generationcircuit 103, 2^(m) digital values, among 2^(n) digital values, which areidentical in the value of the (n−m) most significant bits are allocated.In other words, each of the 2^(n-m) step voltages corresponds to (n−m)bit precision.

The smallest digital value among the 2^(m) digital values for each stepvoltage is allocated to the first step of the step voltage, the secondsmallest digital value is allocated to the second step of the stepvoltage, and the largest digital value is allocated to the final(2^(m)-th) step of the step voltage. In other words, in each of the2^(n-m) step voltages, the voltage value increases stepwise each by onelevel of gradation in n-bit precision.

To generate such step voltages, in the step voltage generation circuit103, 2^(m) digital values, among 2^(n) digital values, which areidentical in the value of the (n−m) most significant bits are allocatedto each of the 2^(n-m) synthesis sections. Each of the 2^(n-m) synthesissections receives 2^(m) voltages corresponding to the 2^(m) digitalvalues and sequentially selects the 2^(m) voltages in ascending order ofthe voltage value.

In this embodiment, the voltage values for the steps of each stepvoltage are equivalent to the target voltage values corresponding to thedigital values allocated to the respective steps. In other words, inthis embodiment, each of the 2^(n-m) synthesis sections receives 2^(m)reference voltages corresponding one-to-one to the 2^(m) digital values.Assuming herein that n=10 and m=2, four digital values each having avalue of the eight most significant bits of “00000001” are allocated tostep voltage SV2. The voltages for the respective steps of the stepvoltage SV2 are as follows.

First step: Reference voltage V4 (target voltage value corresponding todigital value “0000000100”)

Second step: Reference voltage V5 (target voltage value corresponding todigital value “0000000101”)

Third step: Reference voltage V6 (target voltage value corresponding todigital value “0000000110”)

Fourth step: Reference voltage V7 (target voltage value corresponding todigital value “0000000111”)

The output times (settling times) for the respective steps of the stepvoltage are determined with the pulses of the clock signal CLK. Forexample, the step voltage generation circuit 103 starts output of avoltage that is to be the first step of a step voltage insynchronization with the rising edge of the reference pulse of the clocksignal CLK, and stops the output of the voltage for the first step ofthe step voltage and also starts output of a voltage that is to be thesecond step of the step voltage in synchronization with the rising edgeof the additional pulse occurring next to the reference pulse. In thiscase, the settling time for the first step of the step voltage isdetermined with the rising edge of the reference pulse and the risingedge of the additional pulse. For example, assuming that m=2, thesettling times for the steps of a step voltage can be determined asfollows.

First-step settling time Set 1: Time period from reference pulse Pr toadditional pulse Pa1

Second-step settling time Set 2: Time period from additional pulse Pa1to additional pulse Pa2

Third-step settling time Set 3: Time period from additional pulse Pa2 toadditional pulse Pa3

Fourth-step settling time Set 4: Time period from additional pulse Pa3to additional pulse Pa4

In the switch 107, the output time period of a step voltage isdetermined in advance for each of 2^(m) digital values (m-bit digitalvalues). For example, for the smallest digital value among the 2^(m)digital values, it is determined that “the step voltage is outputted forthe time period from the rising edge of the reference pulse of the clocksignal CLK to the rising edge of the next-occurring additional pulse”.For example, assuming that m=2, the output time periods of a stepvoltage for respective digital values are determined as follows.

Digital value “00”: Time period from reference pulse Pr to additionalpulse Pa1

Digital value “01”: Time period from reference pulse Pr to additionalpulse Pa2

Digital value “10”: Time period from reference pulse Pr to additionalpulse Pa3

Digital value “11”: Time period from reference pulse Pr to additionalpulse Pa4

FIG. 3 shows the entire configuration of a liquid crystal displaydevice. The liquid crystal display device includes a liquid crystalpanel 20, a gate driver 30 and the drive device 10 shown in FIG. 1. Inthe liquid crystal panel 20, a plurality of liquid crystal capacitances(load capacitances) 21 are placed in a matrix, and a plurality of gatelines G1, G2, G3, . . . and a plurality of source lines S1, S2, S3, . .. are placed. The drive device 10 includes a plurality of DAC circuits110 corresponding to the plurality of source lines S1, S2, S3, . . . .Each of the plurality of DAC circuits 110 supplies its output voltagehaving a voltage value corresponding to the digital value of gradationdata D-DATA to the source line corresponding to the DAC circuit. Thegate driver 30 sequentially selects the gates lines G1, G2, G3, . . . ofthe liquid crystal panel 20 to turn ON transistors connected to eachselected gate line. In this way, the output voltage from each DACcircuit 110 is supplied to a liquid crystal capacitance 21 via thecorresponding source line.

Next, the operation of the drive device of FIG. 1 will be described withreference to FIG. 4. It is herein assumed that n=10 and m=2 and that thedigital value of the gradation data D-DATA given to the latch circuit104 is “0000000110”.

First, the step voltage generation circuit 103 generates 2¹⁰⁻² stepvoltages SV1, SV2, SV3, . . . in synchronization with the clock signalCLK. Each of the step voltages SV1, SV2, SV3, . . . changes in voltagevalue in 2² steps.

The latch circuit 40 receives the gradation data D-DATA and outputs thedigital value of the eight most significant bits of the data,“00000001”, to the selection circuit 105 and the value of the two leastsignificant bits thereof, “10”, to the switch 107.

The selection circuit 105 selects the step voltage SV2 corresponding tothe digital value “00000001” received from the latch circuit 104. Thebuffer 106 amplifies the step voltage SV2 selected by the selectioncircuit 105.

The switch 107 outputs the step voltage SV2 received from the buffer 106for the time period corresponding to the digital value “10” receivedfrom the latch circuit 104 (i.e., the time period from the rising edgeof the reference pulse Pr to the rising edge of the additional pulse Pa3in the clock signal CLK). Hence, the voltage value of the output voltageVout rises up to the voltage value V4 within the settling time Set1, upto the voltage value V5 within the settling time Set2 and up to thevoltage value V6 within the settling time Set3. Once the rising edge ofthe additional pulse Pa3 occurs in the clock signal CLK, the switch 107stops the output of the step voltage SV2. In this way, the voltage valueof the output voltage Vout is finally equal to the voltage value of thereference voltage V6. In other words, the output voltage Vout having thetarget voltage value (voltage value of the reference voltage V6)corresponding to the digital value “0000000110” is supplied to the loadcapacitance 21 of the liquid crystal panel.

With the above configuration, in which it is unnecessary to provide asample/hold circuit between the selection circuit 105 and the buffer106, the time constant in the signal path from the reference voltagegeneration circuit 101 to the buffer 106 can be reduced. Hence, the timeconstant in the signal path from the reference voltage generationcircuit 101 to the load capacitance 21 can be widely reduced. Thispermits speedup of the response of the output voltage as well asreduction in circuit scale. The settling error can therefore be reduced.

Also, since the load capacitance 21 of the liquid crystal panel isnormally as large as several tens of pF, the influence of switch fieldthrough noise due to the switch 107 can be neglected. The size of theswitch 107 can therefore be increased to reduce the ON resistance, andhence the time constant in the signal path from the buffer 106 to theload capacitance 21 can be reduced.

Moreover, it is unnecessary to reduce the resistance value of thereference voltage generation circuit for reducing the time constant inthe signal path from the reference voltage generation circuit 101 to theload capacitance 21 (the time constant of the output voltage). Hence, noconcern for increase in power consumption is necessary.

Embodiment 2

A drive device of Embodiment 2 of the present invention is substantiallythe same in configuration as the drive device of FIG. 1 but is differenttherefrom in the processing by the clock generation circuit 102 and thestep voltage generation circuit 103.

The clock generation circuit 102 generates a clock signal CLK′ in whichthe time period equivalent to the settling time for the first step of astep voltage (time period determined with the reference pulse and thefirst additional pulse) is longer than each of the (2^(m)−1) timeperiods equivalent to the settling times for the (2^(m)−1) steps of thestep voltage (each of the (2^(m)−1) time periods determined with the2^(m) additional pulses).

In synchronization with the clock signal, the step voltage generationcircuit 103 generates 2^(n-m) step voltages in which the first settlingtime is longer than each of the second and subsequent settling times.Also, while the voltage value for the first step of a step voltage isequivalent to the target voltage value corresponding to the digitalvalue allocated to the first step, the voltage values for the second andsubsequent steps of the step voltage are equivalent to voltage valuesobtained by adding an emphasis amount α to the target voltage valuescorresponding to the digital values allocated to the respective steps.

Referring to FIG. 5, the step voltages in this embodiment will bedescribed. In this embodiment, the voltage value for the first step of astep voltage is the target voltage value corresponding to the digitalvalue allocated to the first step. The voltage values for the second andsubsequent steps of the step voltage are voltage values obtained byadding an “emphasis amount α” to the “target voltage valuescorresponding to the digital values allocated to the respective steps”.

To generate such step voltages, each of the 2^(n-m) synthesis sectionsof the step voltage generation circuit 103 receives a voltage indicatingthe target voltage value corresponding to the first step of the stepvoltage (i.e., the reference voltage) and also receives (2^(m)−1)voltages corresponding to the (2^(m)−1) steps other than the first step.The voltage values of the (2^(m)−1) voltages are equivalent to voltagevalues obtained by adding the emphasis amount a to the respective targetvoltage values.

Assuming that n=10 and m=2, four digital values each having a value ofthe eight most significant bits of “00000001” are allocated to stepvoltage SV2. When “emphasis amount α”=“voltage value of one level ofgradation”, the voltage values for the respective steps of the stepvoltage SV2 are as follows:

First step: Reference voltage V4 (target voltage value corresponding todigital value “0000000100”)

Second step: Reference voltage V6 (target voltage value (V5)corresponding to digital value “0000000101”+emphasis amount α)

Third step: Reference voltage V7 (target voltage value (V6)corresponding to digital value “0000000110”+emphasis amount α)

Fourth step: Reference voltage V8 (target voltage value (V7)corresponding to digital value “0000000111”+emphasis amount α)

The control of the settling time for each step of the step voltage andthe output time period of the step voltage is executed followingsubstantially the same procedure as that in Embodiment 1. In thisembodiment, however, the time period equivalent to the settling time forthe first step of the step voltage in the clock signal CLK is extended.The settling time Sell is therefore longer than that in FIG. 2 and thesettling times Set2, Set3 and Set4 are shorter than those in FIG. 2.Also, the output time periods of the step voltage corresponding to the mleast significant bits are longer than those in FIG. 2.

Next, the operation of the drive device of this embodiment will bedescribed with reference to FIGS. 6A and 6B. Note that the descriptionwill be made taking the case of output of the step voltage SV2 as anexample.

As the time constant of the output voltage Vout is greater, the riserate of the voltage value of the output voltage Vout is slower. Hence,the time required for the output voltage Vout to reach the voltage valuefor each step of the step voltage is longer. When the settling timesSet1, Set2, Set3 and Set4 for the steps of the step voltage are equal toone another as in FIG. 6A, the voltage value may possibly shift from thefirst step to the second step in the step voltage SV2 before the outputvoltage Vout reaches the voltage value for the first step of the stepvoltage SV2, causing a settling error in the first step of the stepvoltage.

When the settling time Sell for the first step of the step voltage islonger than the other settling times Set2, Set3 and Set4 as in FIG. 6B,the output voltage Vout can reach the voltage value for the first stepof the step voltage SV2 within the settling time Set1. Hence, thesettling error in the first step of the step voltage can be reduced.Moreover, since the voltage values for the second and subsequent stepsof the step voltage are higher than the respective target voltagevalues, the rise rate of the output voltage Vout can be increased.Hence, the settling error in these steps of the step voltage can bereduced.

Hereinafter, the relationship between the digital value and the voltagevalue of the output voltage will be described with reference to FIG. 7.In the case of FIG. 6A, if the settling error in the first stage of thestep voltage is great, the linear relationship between the digital valueand the voltage value of the output voltage will be broken (“repeatcode” phenomenon). Instead, the relationship between the digital valueand the voltage value of the output voltage will be like line Line1.

In the case of FIG. 6B, in which the settling error in the first step ofthe step voltage can be reduced, the (n−m) bit precision that is coarserthan n-bit precision can be improved, and thus the monotonous increasecharacteristic of the output voltage can be ensured. Moreover, in eachof the second and subsequent steps of the step voltage, since the riserate of the output voltage Vout can be increased, the output voltageVout is allowed to reach the target voltage value even though thesettling time is short. Hence, the relationship between the digitalvalue and the voltage value of the output voltage is linear like Line 2,preventing occurrence of “repeat code”. In this way, not only the (n−m)bit precision but also the n-bit precision can be improved.

As described above, by increasing the settling time for the first stepof the step voltage, the voltage value of the output voltage is allowedto reach the voltage value for the first step within the settling timefor the first step. With this, the settling error can be reduced andthus occurrence of “repeat code” is prevented. In this way, with thefunction as the DAC being kept from failing, this embodiment issufficiently applicable to an application for which no ultra-highprecision linearity is required.

Also, by making the voltage values for the second and subsequent stepshigher than the respective target voltage values, the rise rate of thevoltage value of the output voltage can be increased. Hence, the voltagevalue of the output voltage is allowed to reach the target voltagevalues within the respective settling times, and thus the linearitybetween the digital value and the voltage value of the output voltagecan further be improved.

Moreover, since no sample/hold circuit is connected upstream of thebuffer 106 and the size of the switch 107 can be increased, the relativeprecision of the signal path from the buffer 106 to the load capacitance21 can be improved, and this can reduce variations in the time constantof the output voltage among the plurality of DAC circuits 110. Hence,the time constant of the output voltage can be considered same among theplurality of DAC circuits 110, and this makes it easy to set theemphasis amount for the respective DAC circuits.

Note that in the settling time for the first step, the settling errorshould preferably be converged to within ½ LSB (less significant bit) inn-bit precision. In other words, the settling error should preferably beconverged to within a potential difference equivalent to a half of onelevel of gradation in n-bit precision.

The length of the settling time for the first step of the step voltagemay be set, considering the time constant of the output voltage, so thatthe voltage value of the output voltage can reach (or be close to) thevoltage value for the first step within the settling time for the firststep.

The emphasis amount a added for the second and subsequent steps of thestep voltage is not limited to the voltage value corresponding to onelevel of gradation in n-bit precision. The emphasis amount a may be set,considering the time constant of the output voltage and the settlingtime for each step of the step voltage, so that the voltage value of theoutput voltage can reach (or be close to) the target voltage valuewithin the settling time for each of the second and subsequent steps.

To each of the 2^(n-m) synthesis sections of the step voltage generationcircuit 103, (2^(m)−1) reference voltages are supplied as the (2^(m)−1)voltages for the second and subsequent steps of a step voltage.Alternatively, as the (2^(m)−1) voltages, not the reference voltagesgenerated by the reference voltage generation circuit 101 but voltagesgenerated by another voltage generation circuit may be used.

Embodiment 3

FIG. 8 shows a configuration of a drive device of Embodiment 3 of thepresent invention. The drive device 10 of this embodiment is the same inconfiguration as that of FIG. 1 except for including a clock generationcircuit 302 and a step voltage generation circuit 303 in place of theclock generation circuit 102 and the step voltage generation circuit 103shown in FIG. 1.

The clock generation circuit (settling time adjustment section) 302adjusts the length of the time period equivalent to the settling timefor the first step of a step voltage in the clock signal CLK′ accordingto time constant information InfoK. The time constant information InfoKis information on the time constant of the output voltage (time constantin the signal path from the reference voltage generation circuit 101 tothe load capacitance 21), which is the row number of a gate lineselected by the gate driver 30, for example.

The step voltage generation circuit 303 adjusts the emphasis amount a tobe added to the second and subsequent steps of the step voltageaccording to the time constant information InfoK. More specifically, thestep voltage generation circuit 303 includes a switch circuit (emphasisadjustment section) 331 in addition to the components of the stepvoltage generation circuit 103 shown in FIG. 1. The switch circuit 331supplies 2 ^(m) reference voltages to each of the 2^(n-m) synthesissections. In other words, the switch circuit 331 supplies, to each ofthe 2^(n-m) synthesis sections, a voltage indicating the target voltagevalue corresponding to the first step of a step voltage (i.e., thereference voltage) and also (2^(m)−1) voltages corresponding to the(2^(m)−1) steps other than the first step. The voltage value of each ofthe (2^(m)−1) voltages is equivalent to a voltage value obtained byadding the emphasis amount α to the corresponding target voltage value.The switch circuit 331 also updates the voltage values of the (2^(m)−1)voltages supplied to each of the 2^(n-m) synthesis sections according tothe time constant information InfoK. In other words, the switch circuit331 adjusts the emphasis amount a according to the time constantinformation InfoK.

Next, the relationship between the magnitude of the time constant andthe length of the settling time for the first step of a step voltage, aswell as the relationship between the magnitude of the time constant andthe emphasis amount for each step of the step voltage, will bedescribed. Note herein that in FIG. 3 the gate lines G1, G2, G3, . . .have sequential row numbers assigned in ascending order starting fromthe one closest to the drive device 10.

As shown in FIG. 3, a plurality of liquid crystal capacitances (loadcapacitances) 21 are connected to each of the source lines S1, S2, S3, .. . . The source line for connecting a liquid crystal capacitance 21with the corresponding DAC circuit 110 is longer as the liquid crystalcapacitance 21 is more distant from the DAC circuit 110, and thus thetime constant of the output voltage supplied to this liquid crystalcapacitance is greater. In other words, as the row number of the gateline selected by the gate driver 30 is greater, the time constant of theoutput voltage is greater.

In the clock generation circuit 302, the settling time for the firststep of a step voltage is determined in advance for each row number. Forexample, as the row number is greater, the settling time for the firststep for the row number is longer.

In the step voltage generation circuit 303, the emphasis amount isdetermined in advance for each row number. For example, as the rownumber is greater, the emphasis amount for the row number is greater.

The operation of the drive device of FIG. 8 will be described withreference to FIGS. 9A and 9B. Note that the description will be madetaking the case of output of the step voltage SV2 as an example.

First, as in FIG. 9A, assume that the length of the settling time forthe first step of the step voltage SV2 is “P1”, and the emphasis amounta for each of the second and subsequent steps of the step voltage SV2 isthe “voltage value of one level of gradation”. In this case, the switchcircuit 331 supplies the reference voltage V4 corresponding to the firststep of the step voltage SV2 and the reference voltages V6, V7 and V8corresponding to the subsequent three steps of the step voltage SV2(reference voltages higher in voltage value than the reference voltagesV5, V6 and V7 as their target voltage values by one level of gradation).At this time, assume also that the gate driver 30 is selecting the gateG2, that is, the row number indicated as the time constant informationInfoK is “2”.

In the state described above, once the gate driver 30 selects the gateline G3, the row number indicated as the time constant information InfoKbecomes “3”. At this time, the clock generation circuit 302 changes thelength of the time period equivalent to the settling time Set1 for thefirst step of the step voltage in the clock signal CLK from “P1” to “P2”that is longer than P1. Also, the step voltage generation circuit 303changes the emphasis amount a from the “voltage value of one level ofgradation” to the “voltage value of two levels of gradation”. In otherwords, the switch circuit 331 supplies the reference voltages V7, V8 andV9 (reference voltages higher in voltage value than their referencevoltages V5, V6 and V7 by two levels of gradation), in place of thereference voltages V6, V7 and V8, to the synthesis section 131-2. Inthis way, as shown in FIG. 9B, the settling time Sell for the first stepof the step voltage SV2 is made long, and the voltage values for thesecond and subsequent steps of the step voltages SV2 are made high.Hence, even when the distance to the load capacitance 21 becomes longincreasing the time constant of the output voltage, increase in settlingerror can be suppressed because the settling time for the first step ofthe step voltage and the emphasis amount a for the second and subsequentsteps of the step voltage are made large.

As described above, by adjusting the settling time for the first stepaccording to the change in the magnitude of the time constant of theoutput voltage, increase in settling error in the first step of a stepvoltage can be suppressed, and thus the monotonous increasecharacteristic of the output voltage can be ensured with reliability.

Also, by adjusting the emphasis amount added to each of the second andsubsequent steps of the step voltage according to the change in themagnitude of the time constant of the output voltage, the improvement ofthe bit precision can be maintained.

Note that if only the time constant of the output voltage is previouslyknown for each row number, it is possible to associate in advance thesettling time for the first step of a step voltage and the emphasisamount a to be added to each of the second and subsequent steps of thestep voltage with the time constant information.

Embodiment 4

The drive device of Embodiment 4 of the present invention hassubstantially the same configuration as that of FIG. 1 but is differenttherefrom in the processing by the step voltage generation circuit 103.

In each of the 2^(n-m) step voltages generated by the step voltagegeneration circuit 103, the first-step voltage value is equivalent to avoltage value obtained by adding an emphasis amount β to the targetvoltage value corresponding to the digital value allocated to the firststep, and the second and subsequent-step voltage values are equivalentto voltage values obtained by adding an emphasis amount α to the targetvoltage values corresponding to the digital values allocated to thesesteps.

Referring to FIG. 10, the step voltage in this embodiment will bedescribed. In this embodiment, each of the 2^(n-m) synthesis sections ofthe step voltage generation circuit 103 receives a voltage correspondingto the first step of the step voltage (a voltage having a voltage valueobtained by adding the emphasis amount β to the target voltage value)and (2^(m)−1) voltages corresponding to the (2^(m)−1) steps other thanthe first step (voltages having voltage values obtained by adding theemphasis amount a to the respective target voltage values).

Assuming that n=10 and m=2, four digital values each having a value ofthe eight most significant bits of “00000001” are allocated to the stepvoltage SV2. If “emphasis amount β”=“voltage value of three levels ofgradation” and “emphasis amount α”=“voltage value of one level ofgradation”, the voltage values for the respective steps of the stepvoltage SV2 are expressed as follows:

First step: Reference voltage V7 (target voltage value (V4)corresponding to digital value “0000000100”+emphasis amount β)

Second step: Reference voltage V6 (target voltage value (V5)corresponding to digital value “0000000101”+emphasis amount α)

Third step: Reference voltage V7 (target voltage value (V6)corresponding to digital value “0000000110”+emphasis amount α)

Fourth step: Reference voltage V8 (target voltage value (V7)corresponding to digital value “0000000111”+emphasis amount α)

The control of the settling time for each step of the step voltage andthe output time period of the step voltage is executed in substantiallythe same manner as that in Embodiment 1.

Next, with reference to FIG. 10, the operation of the drive device ofthis embodiment will be described. Note that the description will bemade taking the case of output of the step voltage SV2 as an example.

As shown in FIG. 10, the voltage value for the first step of the stepvoltage SV2 is higher than the target voltage value. Hence, the riserate of the voltage value of the output voltage Vout in the settlingtime Set1 can be increased, allowing the output voltage Vout to reachthe target voltage value for the first step of the step voltage withinthe settling time Set1. Hence, the settling error in the first step ofthe step voltage can be reduced. Moreover, as in the case of FIG. 6B,the voltage values for the second and subsequent steps of the stepvoltage are higher than the respective target voltage values. Hence, thesettling error in the respective steps of the step voltage can bereduced.

As described above, by making the voltage value for the first step of astep voltage higher than the target voltage value, the voltage value ofthe output voltage is allowed to reach the target voltage value for thefirst stage within the settling time for the first step. With this, thesettling error can be reduced and thus occurrence of “repeat code” isprevented.

As in the drive device of Embodiment 2, the clock generation circuit maybe configured to generate the clock signal CLK′ in which the time periodequivalent to the settling time for the first step of a step voltage islonger than each of the (2^(m)−1) time periods equivalent to thesettling times for the (2^(m)−1) steps of the step voltage. In thiscase, the step voltage and the output voltage will be as shown in FIG.11. Having this configuration, the settling error can further besuppressed compared with the case of the drive device of Embodiment 2.That is, even when extension of the settling time for the first step ofthe step voltage is restricted, the settling error in the first step canbe suppressed by adjusting the emphasis amount β added to the first stepof the step voltage.

Also, as in the drive device of FIG. 8, the emphasis amount β added tothe first step of the step voltage may be adjusted according to timeconstant information.

Embodiment 5

FIG. 12 shows a configuration of a drive device of Embodiment 5 of thepresent invention. The drive device 10 of this embodiment furtherincludes a converter circuit 501 in addition to the components of thedrive device 10 of FIG. 1. In the drive device 10 of this embodiment,the voltage value of the output voltage corresponding to each digitalvalue is previously known, and the digital value of digital data iscorrected so that the linear relationship is maintained between thedigital value and the output voltage.

The converter circuit 501 corrects the digital value of received digitaldata based on a lookup table prepared in advance, and outputs thedigital value of the (n−m) most significant bits of the correcteddigital data to the clock generation circuit 102 and the digital valueof the m least significant bits of the corrected digital data to theswitch 107.

The lookup table will be described with reference to FIGS. 13A, 13B and13C. Note that in FIGS. 13A, 13B and 13C, the digital values and thecorrected digital values are expressed in decimal notation forsimplification of description.

As in FIG. 13A, the relationship between the digital value and thevoltage value of the actual output voltage fails to exhibit monotonousincrease in some portions (digital values “8”, “12”, “16” and “20” inFIG. 13A) in some cases. In view of this, as in FIG. 13B, the voltagevalues of the actual output voltage are sorted in ascending order, andthe digital values corresponding to the sorted voltage values of theoutput voltage are given as corrected digital values. As in FIG. 13C,the corrected digital values and digital values arranged in ascendingorder from the minimum value are put in one-to-one correspondence. Inthis way, a lookup table is prepared in which the “digital values” areassociated with the “corrected digital values having linear relationshipwith the voltage values of the actual output voltage”.

Referring to FIG. 14, the relationship between the digital value and theoutput voltage will be described. When no correction is made for thedigital value, “repeat code” may occur, resulting in exhibiting arelationship between the digital value and the voltage value of theoutput voltage like line Line1. In reverse, when the correction is made,the relationship between the digital value and the voltage value of theoutput voltage is like line Line5, in which the monotonous increasecharacteristic of the voltage value of the output voltage can be securedand thus occurrence of “repeat code” can be prevented.

As described above, with the linear relationship between the digitalvalue and the voltage value of the output voltage, the settling errorcan be reduced, and thus the monotonous increase characteristic of theoutput voltage can be secured.

Other Embodiments

In Embodiments 2 to 5 described above, in place of the switch 107connected downstream of the buffer 106, a sample/hold circuit composedof the switch 107 and a sample capacitor 111 may be provided between theselection circuit 105 and the buffer 106. FIGS. 15 to 18 respectivelyshow alterations of Embodiments 2 to 5 having such a configuration.

FIG. 15 shows an alteration of the drive device of Embodiment 2. In thedrive device of FIG. 15, also, the effect of securing the monotonousincrease characteristic of the output voltage can be obtained byincreasing the settling time for the first step of each step voltage.Moreover, the effect of improving the linearity between the digitalvalue and the voltage value of the output voltage can be obtained byincreasing the voltage values for the second and subsequent steps of thestep voltage.

FIG. 16 shows an alteration of the drive device of Embodiment 3. In thedrive device of FIG. 16, also, the effect of suppressing the increase insettling error can be obtained by adjusting the settling time for thefirst step of each step voltage according to the change in the magnitudeof the time constant of the output voltage. Moreover, the effect ofmaintaining the linearity between the digital value and the voltagevalue of the output voltage can be obtained by adjusting the emphasisamount for each step of the step voltage according to the change in themagnitude of the time constant of the output voltage.

FIG. 17 shows an alteration of the drive device of Embodiment 4. In thedrive device of FIG. 17, also, the effect of reducing the settling errorcan be obtained by making the voltage value for the first step of eachstep voltage higher than the target voltage value. It is also possibleto adjust the emphasis amounts α and β individually according to thechange in the magnitude of the time constant of the output voltage ifonly the step voltage generation circuit 103 is configured like the stepvoltage generation circuit 303 shown in FIG. 16.

FIG. 18 shows an alteration of the drive device of Embodiment 5. In thedrive device of FIG. 18, also, the effect of securing the monotonousincrease characteristic of the output voltage can be obtained bycorrecting the digital value so that the relationship between thedigital value and the voltage value of the output voltage is linear.

INDUSTRIAL APPLICABILITY

As described above, the present invention is useful as a digital/analogconverter circuit used for a drive device for driving a load capacitanceof a liquid crystal panel and the like.

1. A digital/analog converter circuit for generating an output voltagehaving a voltage value corresponding to a digital value of digital dataand supplying the output voltage to a load capacitance as an object tobe driven, the digital/analog converter circuit comprising: a selectionsection for selecting a step voltage, among a plurality of step voltageseach having a voltage value changing stepwise, corresponding to thedigital value of the digital data; an amplifier section for amplifyingthe step voltage selected by the selection section; and an outputsection for supplying the step voltage amplified by the amplifiersection as the output voltage for a time period corresponding to thedigital value of the digital data, wherein for each of the plurality ofstep voltages, different digital values are allocated to different stepsof the step voltage.
 2. The digital/analog converter circuit of claim 1,wherein for each of the plurality of step voltages, a settling time forthe first step of the step voltage is longer than a settling time foreach of the second and subsequent steps of the step voltage.
 3. Thedigital/analog converter circuit of claim 2, wherein for each of theplurality of step voltages, a voltage value for the first step of thestep voltage is higher than a target voltage value corresponding to adigital value allocated to the first step.
 4. The digital/analogconverter circuit of claim 3, wherein for each of the plurality of stepvoltages, voltage values for the second and subsequent steps of the stepvoltage are higher than target voltage values corresponding to digitalvalues allocated to these steps.
 5. The digital/analog converter circuitof claim 4, further comprising an emphasis adjustment section foradjusting, for each of the plurality of the step voltages, the voltagevalues for the second and subsequent steps of the step voltage accordingto the magnitude of a time constant of the output voltage.
 6. Thedigital/analog converter circuit of claim 3, further comprising anemphasis adjustment section for adjusting, for each of the plurality ofthe step voltages, the voltage value for the first step of the stepvoltage according to the magnitude of a time constant of the outputvoltage.
 7. The digital/analog converter circuit of claim 2, wherein foreach of the plurality of step voltages, voltage values for the secondand subsequent steps of the step voltage are higher than target voltagevalues corresponding to digital values allocated to these steps.
 8. Thedigital/analog converter circuit of claim 7, further comprising anemphasis adjustment section for adjusting, for each of the plurality ofthe step voltages, the voltage values for the second and subsequentsteps of the step voltage according to the magnitude of a time constantof the output voltage.
 9. The digital/analog converter circuit of claim2, further comprising a settling time adjustment section for adjusting,for each of the plurality of the step voltages, the settling time forthe first step of the step voltage according to the magnitude of a timeconstant of the output voltage.
 10. The digital/analog converter circuitof claim 1, wherein for each of the plurality of step voltages, avoltage value for the first step of the step voltage is higher than atarget voltage value corresponding to a digital value allocated to thefirst step.
 11. The digital/analog converter circuit of claim 10,wherein for each of the plurality of step voltages, voltage values forthe second and subsequent steps of the step voltage are higher thantarget voltage values corresponding to digital values allocated to thesesteps.
 12. The digital/analog converter circuit of claim 11, furthercomprising an emphasis adjustment section for adjusting, for each of theplurality of the step voltages, the voltage values for the second andsubsequent steps of the step voltage according to the magnitude of atime constant of the output voltage.
 13. The digital/analog convertercircuit of claim 10, further comprising an emphasis adjustment sectionfor adjusting, for each of the plurality of the step voltages, thevoltage value for the first step of the step voltage according to themagnitude of a time constant of the output voltage.
 14. Thedigital/analog converter circuit of claim 1, further comprising aconversion section for converting the digital value of the digital datato a corrected digital value whose correspondence with the voltage valueof an actual output voltage is linear, wherein the selection sectionselects a step voltage, among the plurality of step voltages,corresponding to the corrected digital value of the digital dataobtained by the conversion section, and the output section outputs thestep voltage from the amplifier section as the output voltage for a timeperiod corresponding to the corrected digital value of the digital dataobtained by the conversion section.
 15. A digital/analog convertercircuit for outputting an output voltage having a voltage valuecorresponding to a digital value of digital data, comprising: aselection section for selecting a step voltage, among a plurality ofstep voltages each having a voltage value changing stepwise,corresponding to the digital value of the digital data; and an outputsection for outputting the step voltage selected by the selectionsection for a time period corresponding to the digital value of thedigital data, wherein for each of the plurality of step voltages,different digital values are allocated to different steps of the stepvoltage, and a settling time for the first step of the step voltage islonger than a settling time for each of the second and subsequent stepsof the step voltage.
 16. The digital/analog converter circuit of claim15, wherein for each of the plurality of step voltages, voltage valuesfor the second and subsequent steps of the step voltage are higher thantarget voltage values corresponding to digital values allocated to thesesteps.
 17. The digital/analog converter circuit of claim 16, furthercomprising an emphasis adjustment section for adjusting, for each of theplurality of step voltages, the voltage values for the second andsubsequent steps of the step voltage according to the magnitude of atime constant of the output voltage.
 18. The digital/analog convertercircuit of claim 15, further comprising a settling time adjustmentsection for adjusting, for each of the plurality of step voltages, thesettling time for the first step of the step voltage according to themagnitude of a time constant of the output voltage.
 19. A digital/analogconverter circuit for outputting an output voltage having a voltagevalue corresponding to a digital value of digital data, comprising: aselection section for selecting a step voltage, among a plurality ofstep voltages each having a voltage value changing stepwise,corresponding to the digital value of the digital data; and an outputsection for outputting the step voltage selected by the selectionsection for a time period corresponding to the digital value of thedigital data, wherein for each of the plurality of step voltages,different digital values are allocated to different steps of the stepvoltage, and a voltage value for the first step of the step voltage ishigher than a target voltage value corresponding to a digital valueallocated to the first step.
 20. The digital/analog converter circuit ofclaim 19, wherein for each of the plurality of step voltages, voltagevalues for the second and subsequent steps of the step voltage arehigher than target voltage values corresponding to digital valuesallocated to these steps.
 21. The digital/analog converter circuit ofclaim 20, further comprising an emphasis adjustment section foradjusting, for each of the plurality of step voltages, the voltagevalues for the second and subsequent steps of the step voltage accordingto the magnitude of a time constant of the output voltage.
 22. Thedigital/analog converter circuit of claim 19, further comprising anemphasis adjustment section for adjusting, for each of the plurality ofstep voltages, the voltage value for the first step of the step voltageaccording to the magnitude of a time constant of the output voltage. 23.A digital/analog converter circuit for outputting an output voltagehaving a voltage value corresponding to a digital value of digital data,comprising: a conversion section for converting the digital value of thedigital data to a corrected digital value whose correspondence with thevoltage value of an actual output voltage is linear; a selection sectionfor selecting a step voltage, among a plurality of step voltages,corresponding to the corrected digital value of the digital dataobtained by the conversion section; and an output section for outputtingthe step voltage selected by the selection section as the output voltagefor a time period corresponding to the corrected digital value of thedigital data obtained by the conversion section.